It is well known in the prior art to employ silicon dioxide (SiO.sub.2) on silicon wafers as a diffusion mask, to protect diffused junctions from impurity contamination, as a surface insulator to separate various devices and metal interconnections, or as a dielectric film for capacitors. The masking properties of SiO.sub.2 are particularly important to prevent positively charged ions, such as Na.sup.+ or H.sup.+, which have relatively large diffusion coefficients in SiO.sub.2 at low temperatures, from entering the doped areas of the wafer which the SiO.sub.2 masks since the sodium and hydrogen ions can be especially detrimental to integrated circuit devices containing lightly doped p-type regions.
SiO.sub.2 can be formed by thermal oxidation of silicon wafers in a diffusion furnace at temperatures between 900.degree. and 1200.degree. Centigrade. Thermal oxidation is carried out by contacting silicon on the wafer surfaces with oxygen or steam. However, the high temperatures required for the growth of thermal oxides can often lead to redistribution of the previously diffused impurity layers. In order to avoid the dopant redistribution, low temperature deposited oxide processes which, for instance, employ the pyrolytic decomposition of tetraethylorthosilicate (TEOS) or which employ vapor phase reactions such as the reaction between silane (SiH.sub.4) and oxygen are desirable since they can typically be run at temperatures of 400.degree. to 500.degree. Centigrade. Such pyrolytic deposition of SiO.sub.2 or silicate glass sometimes referred to as s-glass, can also be used to form a protective dielectric coating over the entire integrated circuit surface after the metal interconnections have been formed.
A typical apparatus for the formation of thermal oxides on silicon wafers is disclosed in U.S. Pat. No. 4,253.417 to Valentijn for CLOSURE FOR THERMAL REACTOR, which is assigned to the assignee of the present application. An improvement to prevent stratification of gases within a high pressure oxidation system is disclosed in U.S. Pat. No. 4,376,796 to Arrasmith et al. for PROCESSING SILICON WAFERS EMPLOYING PROCESSING GAS ATMOSPHERES OF SIMILAR MOLECULAR WEIGHT, which is assigned to the assignee of the present application. A typical system for the formation of deposited oxides on silicon wafers is disclosed in U.S. Pat. No. 4,369,031 to Goldman et al. for GAS CONTROL SYSTEM FOR CHEMICAL VAPOR DEPOSITION SYSTEM which is assigned to the assignee of the instant invention.
In addition, it has been found that it is often important to provide a very uniform deposited oxide coating on the silicon wafers. In order to achieve this, the wafers are often enclosed within a shrouded boat during deposition, as is disclosed in U.S. Pat. No. 4,098,923 to Alberti, et al. for PYROLYTIC DEPOSITION OF SILICON DIOXIDE ON SEMICONDUCTORS USING A SHROUDED BOAT. Alberti, et al. teaches a deposited oxide system which employs oxygen, silane and phosphine as the reactants to deposit a phosphosilicate glass. The deposition process takes place at a pressure of less than 50 microns and at a deposition rate of 100 Angstroms per minute.
Phosphosilicate or phosphorus doped glass is employed as a flow glass layer in the production of semiconductors. In other words, it comprises an inert insulating layer which, when deposited, assumes the contours of the surface upon which it is deposited. Since it is well known that integrated circuits often have a terraced surface contour due to previous deposition and etching steps and that metal interconnects are often formed on the top of such a deposited glass layer, it is desirable to flow or slightly soften the glass in an additional flow step wherein the silicon wafers are subjected to an elevated temperature in order to soften the contours of the glass. If such a flow step is not performed and aluminum interconnect layers are formed directly on the deposited glass layer, there can be failures of the metal interconnects at places where the slope of the glass layer changes abruptly due to the fact that microcracks are formed which can, at the least, raise the resistance of the metal interconnects, or even sever the connection completely. As the geometries of the integrated circuits formed on wafers have reduced, it has become more and more difficult to provide a glass coating having flow characteristics which are compatible with other process steps in order to minimize redistribution of dopants during flow annealing.
The temperature at which the glass softens is determined by the concentration of phosphorus within the glass. Thus, as the concentration of phosphorus is increased, the glass has a tendency to soften at lower temperatures. However, the concentration of phosphorus does have an upper limit, due to the fact that phosphorus atoms can diffuse out of the glass and into the doped portions of the wafers causing changes in the doping concentration and degraded performance or cause failure of the integrated circuit. In addition, the phosphorus in glass is hygroscopic. Its tendency to attract moisture can lead to the formation of phosphoric acid within the glass layer which can damage metal interconnects in contact with the glass.
As an alternative, boron doped glasses have also been employed to lower the flow temperature so that redistribution of dopants does not take place during the flow reheating step. Most recently the art has advanced to the point that a combination of phosphorus and boron included in the glass layer provides low flow temperatures and provides a combination which prevents phosphorus contamination problems and the tendency of the glass layer to absorb water and generate phosphoric acid within itself. Typical of prior art processes for forming borophosphosilicate glass is U.S. Pat. No. 3,481,781 to Kern for SILICATE GLASS COATING OF SEMICONDUCTOR DEVICES. An article entitled "Chemical Vapor-Deposited Borophosphate Glass for Silicon Device Applications" by W. Kern and G. Schnable, published in Volume 43, RCA Review, September, 1982, indicates the importance of the use of borophosphosilicate glass films to provide adequately tapered contours over steep steps of oxide and polycrystalline silicon in order to insure the continuity and maintenance of film thickness of subsequently deposited metal conductor interconnect lines. That article teaches the use of chemical vapor deposition employing silane, diborane (B.sub.2 H.sub.6) and phosphine (PH.sub.3) with oxygen. The article further states that certain rotary batch reactors, continuous oxide deposition reactors and continuous reactors are commercially available for carrying out the disclosed process.
Applicants, in experimenting with the chemical vapor deposition of borophosphosilicate glasses, particularly at low temperatures, employing deposited oxide systems having injector manifolds extending along the length of the process tube of the type disclosed in U.S. Pat. No. 4,369,031, have found that atmospheric pressure chemical vapor deposition systems do not provide the uniformity of film thickness, and the low rates of particle and pinhole formation in the SiO.sub.2 layer which are required of deposited oxide layers by the wafer fabrication industry. In addition, the prior art atmospheric pressure systems appear to produce oxide layers having nonuniform step coverage which causes the process run in an atmospheric pressure system to be nonrepeatable and unreliable.
When applicants began experimenting with reduced pressure, or low pressure injector type CVD systems employing silane, oxygen, phosphine and diborane as reactants, they found that very little boron was included within the deposited glass layer, the diborane apparently, almost completely dissociating within the injector manifold thereby depositing most of the boron within the injector tubes, and depleting the source of boron before it reached the vicinity of the wafers.
What is needed, then, is a low pressure chemical vapor deposition system for depositing deposited glass thin films of borophosphosilicate glass on silicon wafers, the thin films having low flow temperatures, adequate inclusion of boron, good step coverage and few pinholes.